e-Ismosys & ADI Special Edition

Silicon Storage Technology (SST) launch three new industrial temperature grade additions to its NANDrive family of embedded solid-state storage devices; The 12x24x1.4mm ‘Mini' package houses industrial temp grade 512MByte 1GByte, and 2GByte products.

Cynove USB camera modules can be easily adapted to customer requirements at reasonable NRE cost and production quantities start with only 50 units a year. License models for evaluation and prototyping are available via Ismosys.com.

For more information about Cynove and their Products click on the button below and insert "Cynove" in the comments field. 

Are you building next generation packet based infrastructure?

Networks of the near future are going to be faster, more robust and more secure, and will feature the built-in versatility required to adapt to an ever increasing rate of change. To build them, engineers will need a new kind of high performance, resource-rich configurable device, which is why Cswitch developed the Configurable Switch Array, simply the highest performing, lowest power consuming and most versatile configurable solution available today.

Inspired by reality.
New network protocols, growing security concerns, the convergence of triple-play services, evolving technologies and ever-present performance pressures are increasing the complexity of all types of networks, and the rate of change will go on accelerating. To further complicate matters, the equipment needed to manage, sustain, and secure these networks will also have to much more sophisticated. The reality is that network equipment destined for tomorrow’s market will have to be faster, smarter, and more versatile than ever. Which is exactly why Cswitch built the Configurable Switch Array (CSA).

Taking input from the world’s leading networking and storage equipment suppliers Cswitch fashioned a revolutionary device that delivers a rare hat trick combination of performance, low power consumption and 100% reconfigurability. With the CSA designers are able to replace costly and time consuming ASICs, and slow, inadequate FPGAs with a device that exceeds the best advantages of both.

Packet moving, editing and storing.
If a custom chip is to deliver high performance in any type of networks, it has to be able to move, edit and store packets at very high speeds, and that’s exactly what the Configurable Switch Array does. Move: The CSA is the first configurable solution to deliver bandwidth at 40 to 100 Gbps across a broad range of applications enabling it to move up to 6 TBps of packets at speeds of up to 2 GHz. Edit: The CSA packs a rich assortment of Frame Header Parsers, Arithmetic Units, and RCAMs to edit and classify packets at 1 GHz speeds. Store: The CSA includes over 18 Mb of on-chip memory, as well as support for the latest high-speed memories, such as DDR2, RLDRAM2, and QDR2. And with the Cswitch, CSA each of these key elements is uncompromisingly configurable.

Click here to view larger image (pdf)

Configurability and reconfigurability
Conventional chip configurability has always come at a cost, with an expensive trade-off to be found somewhere in the gate density, performance and/or power consumption figures. Not anymore: Featuring over 7 million equivalent ASIC gates, speeds of up to 100 Gbps on chip, and the very latest in power management techniques, the Cswitch Configurable Switch Array delivers uncompromising configurability, and with no trade off in density, performance, or consumption.

A 2 GHz, 20-bit wide bus runs in a grid above all the configurable resources on the surface of the CSA and provides up to 6 TBps of bandwidth to all of the major resource blocks. At each intersection, Cswitch’s innovative dataCrossconnect provides fast on- and off-ramps to speed packets back and forth between the resources and ultimately, across and off the chip. Using the latest advancements in power management the CSA automatically reduces power by shutting off clocks to sectors not in use, enabling designers to vary the chip voltage to achieve the optimum total power requirements.

The capabilities of an ASIC tool with the ease of use and rapid deployment of an FPGA tool.
Thanks to it’s partnership with Magma® Design Automation, Cswitch is continuing to deliver on its commitment to provide customers with a feature-rich design flow that appeals to both ASIC and FPGA developers.

Fully leveraging  the Cswitch CSA architecture, Magma offers a fully automated tool flow from synthesis through placement & route to final bitstream generation. Magma’s Blast Cswitch technology synthesizes the control logic directly to the CSA’s Programmable Logic  Blocks (PLBs). When more complex data path oriented logic is required, Magma tools reach out to the CSA’s switch module generator and instantiator to map these complex structures onto the high-performance special-function resources such as RAUs, RCAMs, PacketParser blocks, and dataCrossconnect. The timing is also impeccable: Magma’s timing-driven router lets engineers close timing, with full back annotation, with the minimum of resource expenditure.

Magna’s Graphical Explorer (geXp) tool provides simple and intuitive GUI displays of designs implemented on the CSA architecture. It displays a floor plan of the chip and highlights the placement of  PLB and custom block (e.g., RAUs, RCAMs) instantiations. PLB and dataCrossconnect routing resources and design nets can also be selectively highlighted. Display pop-up windows can be opened to display the internal configuration of instantiated PLBs or custom blocks while convenient side windows can be opened to show netlist timing data.

One part, many successes.
The recourses and capabilities of the Cswitch Configurable Switch Array make it the most versatile of any configurable solution currently available. In addition, the savings the device provides in both development time and inventory translate directly to the bottom line. This is the CSA reality!

For more information about the Cswitch Configurable Switch Array chip click on the button below and enter "Cswitch" in the text field.

High Performance, ISM Band, FSK/ASK Transceiver IC

Add a few discrete external components and you’ve built a complete transceiver! The Analog Devices ADF7020-1 is a low power, highly integrated FSK/GFSK/ASK/OOK/GOOK transceiver designed for operation in the low UHF and VHF bands.

The ADF7020-1 uses an external VCO (voltage control oscillator) inductor which allows the user to set the operating frequency anywhere between 135MHz and 650MHz. Typical range of the VCO is circa 10% of the operating frequency. The ADF7020-1 is ideal for use in very price-sensitive and area-sensitive applications as only a small number external discrete components are required to build a complete transceiver.

Transmitter
The transmit section of the ADF7020-1 contains a VCO and low noise fractional-N PLL with output resolution of <1 ppm. This frequency-agile PLL enables the ADF7020-1 to be used in frequency hopping spread spectrum (FHSS) systems. The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems.

The transmitter output power is programmable in 0.3 dB steps ranging from −16 dBm to +13 dBm. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The ADF7020-1 operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use.

Receiver
Built with a low IF architecture the 200 kHz receiver in the ADFF7020-1 minimises power consumption and avoids interference problems at low frequencies. The device supports a wide variety of programmable features including Rx linearity, sensitivity, and IF bandwidth, enabling engineers to trade off receiver sensitivity and selectivity against current consumption, to suit the particular application. The receiver also features a patent-pending automatic frequency control (AFC) loop which enables the PLL to track out the frequency error in the incoming signal.

An on-chip ADC provides readback of an integrated temperature sensor, an external analog input, the battery voltage, or the RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to ±10°C over the full operating temperature range of −40°C to +85°C. Increased accuracy is available if the user does a 1-point calibration at room temperature and stores the result in memory.

ADI SRD Design Studio
The ADFF7020-1 is supported by Analog Devices’ ADI SRD Design Studio, a very powerful tool that allows real-time simulation and optimisation of many of the parameters in a typical wireless system. Based on ADI’s popular ADIsimPLL™ tool The ADI SRD Design Studio has been enhanced to allow users to view modulation in both the time and frequency domains.

ADFF7020-1 Key Features
• Low power, low IF transceiver
• Frequency bands: 135 MHz to 650 MHz

• Data rates supported:
            FSK: 0.15 kbps to 200 kbps
            ASK:0.15 kbps to 64 kbps
• 2.3 V to 3.6 V power supply
• Programmable output power: -16 dBm to +13 dBm in 0.3 dBm steps
• Receiver sensitivity
            -119 dBm at 1 kbps, FSK
            -112 dBm at 9.6 kbps, FSK
            -106.5 dBm at 9.6 kbps, ASK
• On-chip VCO and fractional-N PLL
• Low power consumption
           18 mA in receive mode
           27 mA in transmit mode (10 dBm output)
• On-chip 7-bit ADC and temperature sensor
• Fully automatic frequency control loop (AFC) compensates for lower tolerance crystals Digital RSSI
• Integrated TRx switch